-- Register File Architecture
-- Chang Lan, <changlan9@gmail.com>
-- 11/9/2011

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.global_definition.all;

architecture behave of regfile is
    subtype WordT is std_ulogic_vector(width-1 downto 0);
    type    StorageT is array(0 to regfile_depth-1) of WordT;
    signal  registerfile : StorageT;
begin
    -- write
    process(rst_n, clk)
    begin
        if rst_n = '0' then
            for i in 0 to regfile_depth-1 loop
                registerfile(i) <= (others => '0');
            end loop;
        elsif rising_edge(clk) then
            if write_enable = '1' then
                registerfile(TO_INTEGER(unsigned(address_write_port))) <= write_port;
            end if;
        end if;
    end process;

    -- read ports
    read_port_0 <= registerfile(TO_INTEGER(unsigned(address_port_0)));
    read_port_1 <= registerfile(TO_INTEGER(unsigned(address_port_1)));
	
	read_port_ih <= registerfile(TO_INTEGER(unsigned(RegAddr_IH)));
end behave;
